Liquid crystal display devices utilizing amorphous silicon (a-Si) thin film transistors (hereinafter referred to as “a-Si TFTs”) as driver elements have conventionally been known. In recent years, development of liquid crystal display devices utilizing microcrystalline silicon (μc-Si) thin film transistors (hereinafter referred to as “μc-Si TFTs”) as driver elements is moving forward. Mobility of microcrystalline silicon is greater than that of amorphous silicon, and the μc-Si TFTs can be formed by a process similar to that of the a-Si TFTs. For this reason, employment of the μc-Si TFTs as the driver elements is expected to realize such as a cost reduction by decreasing a frame area and by decreasing a number of chips in a driver IC, an improvement of a mounting yield, and an increase in size of display devices. Further, the μc-Si TFTs have a characteristic that a threshold shift (a change in a threshold voltage) when a voltage is applied to a gate electrode for an extended period of time is smaller than that of the a-Si TFTs. In other words, the μc-Si TFTs are more reliable than the a-Si TFTs in that the μc-Si TFTs are insusceptible to degradation.
By the way, a display unit of an active matrix-type liquid crystal display device includes a plurality of source bus lines (video signal lines), a plurality of gate bus lines (scanning signal lines), and a plurality of pixel formation portions respectively provided at intersections of the plurality of source bus lines and the plurality of gate bus lines. These pixel formation portions are arranged in a matrix to constitute a pixel array. Each pixel formation portion includes such as a thin film transistor as a switching element whose gate terminal is connected to the gate bus line that passes the corresponding intersection and whose source terminal is connected to the source bus line that passes the corresponding intersection, and a pixel capacitance for storing a pixel value. Further, such an active matrix-type liquid crystal display device is provided with a source driver (video signal line drive circuit) for driving the plurality of source bus lines and a gate driver (scanning signal line drive circuit) for driving the plurality of gate bus lines.
Video signals indicating pixel values are transferred via the source bus lines. However, it is not possible to transfer video signals indicating pixel values for the plurality of lines at one time (the same time) through a single source bus line. For this reason, the video signals are written to the pixel capacitances in the pixel formation portions arranged in a matrix sequentially line by line. Therefore, the gate driver is configured by a shift register having a plurality of stages so that the plurality of gate bus lines are sequentially selected for a predetermined period.
It is desirable that each gate bus line turns to a selected state only once in one frame period (one horizontal scanning period). Therefore, it is preferable that a scanning signal to be applied to each gate bus line is to be at a potential at a High level only in a period that each gate bus line should be set to the selected state (hereinafter, referred to as a “selection period”) and is fixed at a potential at a Low level in a period other than the selection period (hereinafter, referred to as a “non-selection period”). However, the potential of the scanning signal sometimes varies in a positive direction from the potential at the Low level in the non-selection period under an influence of a parasitic capacitance formed on a circuit that forms the shift register. Thus, Japanese Patent Application Laid-Open No. 2006-351171 discloses an invention concerning a shift register capable of reducing an influence due to a parasitic capacitance as compared with a conventional case. FIG. 15 is a circuit diagram showing a configuration corresponding to one stage in the shift register disclosed in Japanese Patent Application Laid-Open No. 2006-351171. According to this circuit, during a non-selection period, a gate bus line does not turn to a floating state and a gate-off voltage is always supplied to the gate bus line. It is considered that this allows suppression of the influence due to the parasitic capacitance.